MAX5952CUAX+【PDF 38/50 页】IC PSE CNTRLR FOR POE 36-SSOP

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Sheet目录43

34页 35页 36页 37页 [38页]39页 40页 41页 42页

High-Power, Quad, PSE Controller

for Power-Over-Ethernet

38 ______________________________________________________________________________________

The CLC_EN enables the large capacitor detection fea-

ture. When CLC_EN is set the device can recognize a

capacitor load up to 100礔. If the CLC_EN is reset, the

MAX5952 performs normal detection.

AC_TH allows programming of the threshold of the AC

disconnect comparator. The threshold is defined as a

current since the comparators verify that the peak of

the current pulses sensed at the DET_ input exceed a

preset threshold. The current threshold is defined as

follows:

IAC_TH = 226.68礎 + 28.33 x NAC_TH

where NAC_TH is the decimal value of AC_TH.

When set low, DET_BY inhibits port power-on if the dis-

covery detection was bypassed in auto mode. When

set high, DET_BY allows the device to turn on power to

a non-IEEE 802.3af load without doing detection. If

OSCF_RS is set high, the OSC_FAIL bit is ignored. A

reset or power-up sets R23h = 04h. Default IAC_TH is

340礎.

Table 27. Switch Mode Register

ADDRESS = 1Fh

SYMBOL

BIT

R/W

DESCRIPTION

EN_WHDOG

R/W

A logic-high enables the watchdog function

WD_INT_EN

R/W

Enables interrupt on SMODE_ bits

Reserved

R/W

Reserved

HWMODE4

R/W

Port 4 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer

expires

HWMODE3

R/W

Port 3 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer

expires

HWMODE2

R/W

Port 2 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer

expires

HWMODE1

R/W

Port 1 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer

expires

Table 28. Program Register

ADDRESS = 23h

SYMBOL

BIT

R/W

DESCRIPTION

Reserved

CLC_EN

R/W

Large capacitor detection enable

DET_BY

R/W

Enables skipping detection in AUTO mode

OSCF_RS

R/W

OSC_FAIL reset bit

R/W

AC_TH[2]

R/W

AC_TH[1]

AC_TH

R/W

AC_TH[0]

Setting EN_WHDOG (Table 27) high activates the

watchdog counter. When the counter reaches zero, the

port switches to the hardware-controlled mode deter-

mined by the corresponding HWMODE_ bit. A low in

HWMODE_ switches the port into shutdown by setting

the bits in register R12h to 00. A high in HWMODE_

switches the port into auto mode by setting the bits in

sent if any of the SMODE bits are set. A reset sets R1Fh

= 00h.

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